diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index d01e69b..81f7991 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -78,6 +78,7 @@
 	select PHYS_64BIT
 	select ARCH_P3041
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
+	select FSL_NGPIXIS
 	imply CMD_SATA
 	imply PANIC_HANG
 
@@ -86,6 +87,7 @@
 	select PHYS_64BIT
 	select ARCH_P4080
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
+	select FSL_NGPIXIS
 	imply CMD_SATA
 	imply PANIC_HANG
 
@@ -94,6 +96,8 @@
 	select PHYS_64BIT
 	select ARCH_P5040
 	select BOARD_LATE_INIT if CHAIN_OF_TRUST
+	select FSL_NGPIXIS
+	select SYS_FSL_RAID_ENGINE
 	imply CMD_SATA
 	imply PANIC_HANG
 
@@ -262,6 +266,8 @@
 	select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
+	select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
+	select SYS_FSL_USB1_PHY_ENABLE
 	select SYS_PPC64
 	select FSL_IFC
 	imply CMD_EEPROM
@@ -293,6 +299,9 @@
 	select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
+	select SYS_FSL_SRIO_LIODN
+	select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
+	select SYS_FSL_USB1_PHY_ENABLE
 	select SYS_PPC64
 	select FSL_IFC
 	imply CMD_EEPROM
@@ -405,6 +414,7 @@
 	select SYS_FSL_HAS_DDR2
 	select SYS_FSL_HAS_DDR1
 	select SYS_FSL_HAS_SEC
+	select SYS_FSL_RMU
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 	select SYS_PPC_E500_USE_DEBUG_TLB
@@ -440,6 +450,7 @@
 	select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
+	select SYS_FSL_USB1_PHY_ENABLE
 	select SYS_PPC_E500_USE_DEBUG_TLB
 	select FSL_IFC
 	imply CMD_EEPROM
@@ -535,6 +546,7 @@
 	select FSL_PCIE_RESET
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
+	select SYS_FSL_RMU
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 	select SYS_PPC_E500_USE_DEBUG_TLB
@@ -610,6 +622,8 @@
 	select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
+	select SYS_FSL_USB1_PHY_ENABLE
+	select SYS_FSL_USB2_PHY_ENABLE
 	select FSL_ELBC
 	imply CMD_NAND
 
@@ -640,6 +654,8 @@
 	select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
+	select SYS_FSL_USB1_PHY_ENABLE
+	select SYS_FSL_USB2_PHY_ENABLE
 	select FSL_ELBC
 	imply CMD_NAND
 	imply CMD_SATA
@@ -681,6 +697,7 @@
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_QORIQ_CHASSIS1
+	select SYS_FSL_RMU
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
 	select FSL_ELBC
@@ -711,6 +728,8 @@
 	select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
+	select SYS_FSL_USB1_PHY_ENABLE
+	select SYS_FSL_USB2_PHY_ENABLE
 	select SYS_PPC64
 	select FSL_ELBC
 	imply CMD_SATA
@@ -742,6 +761,9 @@
 	select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_5
+	select SYS_FSL_SINGLE_SOURCE_CLK
+	select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
+	select SYS_FSL_USB_DUAL_PHY_ENABLE
 	select FSL_IFC
 	imply CMD_EEPROM
 	imply CMD_NAND
@@ -770,6 +792,9 @@
 	select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_5
+	select SYS_FSL_SINGLE_SOURCE_CLK
+	select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
+	select SYS_FSL_USB_DUAL_PHY_ENABLE
 	select FSL_IFC
 	imply CMD_MTDPARTS
 	imply CMD_NAND
@@ -797,6 +822,9 @@
 	select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_5
+	select SYS_FSL_SINGLE_SOURCE_CLK
+	select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
+	select SYS_FSL_USB_DUAL_PHY_ENABLE
 	select FSL_IFC
 	imply CMD_MTDPARTS
 	imply CMD_NAND
@@ -826,6 +854,9 @@
 	select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
+	select SYS_FSL_SRIO_LIODN
+	select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
+	select SYS_FSL_USB_DUAL_PHY_ENABLE
 	select SYS_PPC64
 	select FSL_IFC
 	imply CMD_SATA
@@ -859,6 +890,9 @@
 	select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
+	select SYS_FSL_SRIO_LIODN
+	select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
+	select SYS_FSL_USB_DUAL_PHY_ENABLE
 	select SYS_PPC64
 	select FSL_IFC
 	imply CMD_SATA
@@ -1147,6 +1181,12 @@
 config FSL_PCIE_RESET
 	bool
 
+config SYS_FSL_RAID_ENGINE
+	bool
+
+config SYS_FSL_RMU
+	bool
+
 config SYS_FSL_QORIQ_CHASSIS1
 	bool
 
@@ -1312,6 +1352,9 @@
 	bool
 	select SYS_FSL_CPC
 
+config FSL_NGPIXIS
+	bool
+
 config SYS_CPC_REINIT_F
 	bool
 	help
@@ -1347,6 +1390,33 @@
 	  Defines the string to utilize when trying to match PCIe device tree
 	  nodes for the given platform.
 
+config SYS_FSL_SINGLE_SOURCE_CLK
+	bool
+
+config SYS_FSL_SRIO_LIODN
+	bool
+
+config SYS_FSL_TBCLK_DIV
+	int
+	default 32 if ARCH_P2041 || ARCH_P3041
+	default 16 if ARCH_P4080 || ARCH_P5040 || ARCH_T4240 || ARCH_B4860 || \
+			ARCH_B4420 || ARCH_T1040 || ARCH_T1042 || \
+			ARCH_T1024 || ARCH_T2080
+	default 8
+	help
+	  Defines the core time base clock divider ratio compared to the system
+	  clock. On most PQ3 devices this is 8, on newer QorIQ devices it can
+	  be 16 or 32. The ratio varies from SoC to Soc.
+
+config SYS_FSL_USB1_PHY_ENABLE
+	bool
+
+config SYS_FSL_USB2_PHY_ENABLE
+	bool
+
+config SYS_FSL_USB_DUAL_PHY_ENABLE
+	bool
+
 config SYS_MPC85XX_NO_RESETVEC
 	bool "Discard resetvec section and move bootpg section up"
 	depends on MPC85xx
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index ffa8b60..1b6cdc4 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -334,9 +334,6 @@
 /*
  * Get timebase clock frequency
  */
-#ifndef CONFIG_SYS_FSL_TBCLK_DIV
-#define CONFIG_SYS_FSL_TBCLK_DIV 8
-#endif
 __weak unsigned long get_tbclk(void)
 {
 	unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c
index 21b35db..bdd7338 100644
--- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c
+++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c
@@ -31,10 +31,6 @@
 	return 0;
 }
 
-#ifndef CONFIG_SYS_FSL_TBCLK_DIV
-#define CONFIG_SYS_FSL_TBCLK_DIV 8
-#endif
-
 void udelay(unsigned long usec)
 {
 	u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000);